Computing and Input/Output (I/O) subsystems often need to pass data to each other. First-In-First-Out (FIFO) buffers are often used to safely pass data from one subsystem to another. The implementation of the FIFOs is straightforward when both subsystems use the same clock domain or same data width.
When the subsystems use different port widths and different data width, things become more complicated. An elastic gear FIFO design is often required in such circumstances. Conventional asynchronous gear FIFO buffer design is composed of an asynchronous FIFO buffer design and a synchronous gear FIFO buffer. Asynchronous FIFO buffer designs usually have 2k locations. In such a design, the write pointer is converted to gray code and then synchronized to the read clock domain before being compared to the read pointer. Clock frequency compensation, FIFO full, and FIFO empty all depend on the pointer difference between the synchronized write pointer and read pointer. This constrains the asynchronous FIFO buffer design to have the same input and output data width. An additional synchronous gear FIFO buffer converter is often required to do the data width conversion that is necessary. Implementing an asynchronous gear FIFO buffer with another asynchronous FIFO buffer plus a synchronous gear FIFO buffer are not area effective and introduce unwanted data latency.